Using GLFSRs for Pseudo-Random Memory BIST
نویسندگان
چکیده
In this work, we present the application of Generalized Linear Feedback Shift Registers (GLFSRs) for generation of patterns for pseudo-random memory Built-In SelfTest (BIST). Recently, it was shown that using GLFSRs as pattern generators for pseudo-random logic tests can increase the fault coverage noticeably in comparison to standard pseudo-random test pattern generators. Since memory faults differ from logic faults, we examined if that is also the case for pseudo-random memory tests. We found that GLFSRs can increase the fault coverage of pseudo-random tests for several fault types, especially for complex faults as stuck-open faults. Thus, the usage of GLFSRs as pattern generators for pseudo-random memory testing is recommended although some area overhead has to be accepted.
منابع مشابه
A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing...
متن کاملHybrid BIST Using an Incrementally Guided LFSR
A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-chip pseudo-random BIST. The hardware overhead is very small as a conventional STUMPS architecture [1] is used with only a small modification to the feedback of the LFSR which allows the tester to incrementally guide the LF...
متن کاملAn Efficient Mixed-mode Bist Technique
We propose a new built-in self-test (BIST) method based on a combination of a pseudo-random test method with a deterministic test. This enables us to reach a high fault coverage in a short test time and with a low area overhead. The main feature of the method is that there are no memory elements to store the deterministic test patterns; the test patterns are being produced by a transformation o...
متن کاملSpecial ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random patterns. While previous work in mixed-mode BIST has focused on developing hardware schemes for more efficiently encoding a given set of deterministic patterns (generated by a conventional ATPG procedure), the approach ta...
متن کاملColumn-matching based mixed-mode test pattern generator design technique for BIST
A novel test-per-clock built-in self-test (BIST) equipment design method for combinational or full-scan sequential circuits is proposed in this paper. Particularly, the test pattern generator is being designed. The method is based on similar principles as are well known test pattern generator design methods, like bit-fixing and bit-flipping. The novelty comprises in proposing a brand new algori...
متن کامل